Parasitic-Aware Optimization of CMOS RF Circuits

In the arena of parasitic-aware design of CMOS RF circuits, efforts are aimed at the realization of true single-chip radios with few, if any, off-chip components. The parasitic-aware RF circuit synthesis techniques described in this book effectively address critical problems in this field.

Dedication. Contributing Authors. Preface. Part I: Background on Parasitic-Aware Optimization. 1: Introduction. 1. Introduction. 2. Overview of Wireless Transceivers. 3. Outline of the Book. 2: Modeling of On-Chip Passive and Active Components. 1. Monolithic Inductors. 2. Monolithic Varactors. 3. MOS Transistors. 3: Parasitic-Aware Optimization. 1. Gradient Decent Optimization. 2. Simulated Annealing. 3. Simulated Annealing with Tunneling Process. 4. Genetic Algorithm (GA). 5. Particle Swarm Optimization (PSO). 6. Post PVT Variation Optimization. Part II: Optimization of CMOS RF Circuits. 4: Optimization of CMOS Low Noise Amplifiers. 1. Low Noise Amplifier. 2. Design of Low Noise Amplifier. 3. Optimization of Low Noise Amplifiers. 5: Optimization of CMOS Mixers. 1. Mixer. 2. Single Balanced Mixer. 3. Double Balanced Mixer. 4. Design of Mixers. 5. Optimization of Mixers. 6: Optimization of CMOS Oscillators. 1. CMOS Oscillators. 2. Phase Noise. 3. Design of VCO. 4. Optimization of CMOS VCO. 7: Optimization of CMOS RF Power Amplifiers. 1. RF Power Amplifiers. 2. Design of Power Amplifier. 3. Optimization of Power Amplifier. 4.POST PVT Optimization. 8: Optimization of Ultra-Wideband Amplifiers. 1. CMOS Ultra-Wideband Amplifiers. 2. Design of CMOS Ultra-Wideband Amplifier. 3. Optimization of CMOS Ultra-Wideband Amplifier. Index.